1. Field of the Invention
Exemplary embodiments of the present disclosure relate to a memory system including a memory buffer, and more particularly, to a memory system including a memory buffer, that is capable of preventing performance degradation which may occur in a data read/write operation for a memory module.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional memory system.
The conventional memory system includes a memory buffer 10, a plurality of memory modules 31 to 34, and a memory controller 20 for controlling a read/write operation of the plurality of memory modules 31 to 34 through the memory buffer 10.
The plurality of memory modules 31 to 34 are included in one memory space 30.
The memory buffer 10 includes a plurality of read FIFOs 11 to 14 and a plurality of write FIFOs 15 to 18.
Each of the read FIFOs 11 stores data read from the corresponding memory module 31, and the data stored in the read FIFO 11 are provided to the memory controller 20.
Each of the write FIFOs 15 stores data received from the memory controller 20, and the data stored in the write FIFO 15 are written to the corresponding memory module 31.
In the memory buffer 10 of the conventional memory system, the read FIFOs 11 and the write FIFOs 15 only serve to temporarily store data when a read request or write command is processed.
Thus, when performance degradation occurs in reading data from a memory module 31 or writing data to a memory module 31, the performance degradation of the memory system cannot be prevented even though the memory buffer 10 exists.
For example, the memory module 31 of FIG. 1 includes a plurality of DRAM chips, and each of the DRAM chips includes a plurality of banks.
In order to perform a read request for two different row addresses included in one bank of the DRAM chip, active-read-precharge operations must be performed on one row address, and active-read operations must be performed on the other row address.
Thus, when a read operation is performed on a plurality of row addresses belonging to the same bank, the read time is inevitably increased.
Therefore, when row addresses included in the same bank of a DRAM chip are successively accessed, performance improvement cannot be expected. Such a problem may occur even during a write operation.
Thus, there is a demand for a memory system including a new memory buffer that is capable of reducing performance degradation which may occur when data is read from or written to the memory module 31.